Developing method of vector synthesis deductive logic for computer systems fault analysis

Abstract

The article is devoted to the development of models and methods for fault analysis for examinate test patterns. Deductive fault simulation of digital devices is the most advanced technology that serves the field of design and testing of modern computer systems. At the same time, fault simulation solves the problem of assessing the quality of the test in the class of single constant defects. However, the computational complexity of obtaining deductive formulas, estimated as n3 , is a rather difficult task for high-dimensional RTL-level functional circuits, so the deductive method is usually used only for digital circuits represented at the gate level. Next, we propose a vector method for synthesis deductive formulas for digital schemes represented by RTL elements. This method became possible due to the element description of any complexity in the form of output states vector for combinational device. The model of xor-relationships between the wonderful logical functions (or, xor, and) of digital objects is improved, which is convoluted into zero-space. It makes possible to solve the problems of design and test, machine learning, search for similarities-differences, and destructive components in processes and phenomena. The advantages of the vector model for a compact description of objects, functions and structures are determined. It is proposed to replace analytical expressions that require algorithmically complex calculating, with vector data structures for describing functional logic. Vector-deductive method for synthesis formulas for transporting input fault lists is proposed. It has a quadratic computational complexity of register operations. The coordinate-vector model of defects is considered, not tied to input variables, which can be used for efficient processing of complex logic circuits when assessing the quality of synthesized tests. An algorithm for the synthesis of deductive vectors is presented, which differs from the known ones in the technological parallel processing simplicity of truth tables and makes it possible to create structural and logical conditions for simulating faults in digital projects of the gate, register and system description levels. An efficient method for the synthesis of a deductive truth table according to the rule L=T⊕F is proposed. It differs from the known ones by using vector-coordinate parallel xor-operation. It provides the transportation of faults through a functional element of arbitrary complexity.